(1) Field of the Invention
The present invention relates to a static semiconductor memory device having memory cells arranged in a matrix, each memory cell comprising two driving transistors connected in intersection, and more particularly to a semiconductor memory device having a bit line selection circuit in each column for receiving a high potential selection signal when selected and for supplying a current to the selected column; in which a discharge path is provided in each bit line selection circuit for rapidly lowering the potential of the selection signal during the transition from a selected state to a nonselected state, whereby the power consumption is reduced and high speed operation is realized.
(2) Description of the Prior Art
In recent years, semiconductor memory devices, especially static RAMs (random access memories) have greatly progressed in high integration, high speed operation, and low power consumption. The development of large memory capacities, however, has led to the demand for even higher speed operation and lower power consumption.
FIG. 1A is a circuit diagram illustrating a main portion of a conventional static bipolar RAM. In FIG. 1A, MC.sub.11, MC.sub.1n, MC.sub.mn, . . . represent memory cells arranged in a matrix having n columns C.sub.1 through C.sub.n and m rows R.sub.1 through R.sub.m.
FIG. 1B is a circuit diagram illustrating the memory cell MC.sub.11 in detail. In FIG. 1B, the memory cell MC.sub.11 consists of two driving transistors Q.sub.11 and Q.sub.12 and two memory storage transistors Q.sub.21 and Q.sub.22. The driving transistor Q.sub.11 and the memory storage transistor Q.sub.21 constitute a multi-emitter transistor. Similarly, the transistors Q.sub.12 and Q.sub.22 constitute another multi-emitter transistor. The collector of the transistor Q.sub.11 is connected to the base of the transistor Q.sub.12. Similarly, the collector of the transistor Q.sub.12 is connected to the base of the transistor Q.sub.11. Thus, the collectors of the transistors Q.sub.11 and Q.sub.12 are connected in intersection with each other. The emitters of the memory storage transistors Q.sub.21 and Q.sub.22 are commonly connected to a negative word line WD.sub.1. Load resistors R.sub.11 and R.sub.12 are respectively connected between the collectors of the transistors Q.sub.11 and Q.sub.12 and a positive word line WD.sub.1.sup.+. Load diodes D.sub.1 and D.sub.2 are respectively connected between the collectors of the transistors Q.sub.11 and Q.sub.12 and the positive word line WD.sub.1.sup.+. When this memory cell MC.sub.11 is selected, only one of the diodes D.sub.1 and D.sub.2 conducts current so as to supply a collector current to one of the memory storage transistors Q.sub.21 and Q.sub.22. Thus, the load diodes D.sub.1 and D.sub.2 contribute to saving power consumption.
The other memory cells have a similar configuration to the memory cell MC.sub.11.
Referring back to FIG. 1A, WD.sub.1.sup.+, . . . , and WD.sub.m.sup.+ represent positive word lines connected to the emitters of word driving transistors TW.sub.1, . . . , and TW.sub.m, respectively. The bases of the word driving transistors TW.sub.1, . . . , and TW.sub.m are adapted to receive word selection signals X.sub.1, . . . , and X.sub.m, respectively. The collectors of the transistors TW.sub.1, . . . , and TW.sub.m are grounded. WD.sub.1.sup.-, . . . , and WD.sub.m.sup.- represent negative word lines, each of which is commonly connected to the emitters of the memory storage transistors, included in the corresponding row, and also to a holding current source (not shown).
(B.sub.11, B.sub.12), . . . , and (B.sub.n1, B.sub.n2) each represents a pair of bit lines connected to the emitters of the driving transistors Q.sub.11, Q.sub.12, . . . in the corresponding column. The bit lines B.sub.11, B.sub.12, . . . , B.sub.n1, and B.sub.n2 are connected to the emitters of transistors TR.sub.11, TR.sub.12, . . . , TR.sub.n1, and TR.sub.n2, respectively. The bases of the transistors TR.sub.11, TR.sub.12, . . . , TR.sub.n1 and TR.sub.n2 are adapted to receive a signal of a reference potential for a reading operation. The signal of the reference potential is supplied from a reference potential setting circuit RC. The collectors of the transistors TR.sub.11, TR.sub.12, . . . , TR.sub.n1 and TR.sub.n2 are grounded. PSA.sub.1, . . . , and PSA.sub.n are pre-sense amplifiers each consisting of a pair of transistors (T.sub.71, T.sub.81), . . . , or (T.sub.7n, T.sub.8n), respectively. The bases of the transistors T.sub.71, T.sub.81, . . . , T.sub.7n, and T.sub.8n are connected to the bit lines B.sub.11, B.sub.12, . . . , B.sub.n1, and B.sub.n2, respectively. The collectors of the transistors T.sub.7n, and T.sub.8n, . . . , Q.sub.7n, and Q.sub.8n are commonly connected to a sense amplifier SA. PLP.sub.1, . . . , and PLP.sub.n represent pull-up circuits for charging up the nonselected bit lines, respectively. Each pull-up circuit comprises a multi-emitter transistor T.sub.61, . . . or T.sub.6n with the first emitter being connected to one of the corresponding pair of bit lines and the second emitter being connected to the other of the bit lines.
BD.sub.1, . . . , and BD.sub.n represent bit driver circuits. The bit driver circuit BD.sub.1 comprises a transistor T.sub.11, a diode DI.sub.1, and a current source IB.sub.1. The emitter of the transistor T.sub.11 is connected to the anode of the diode DI.sub.1. The cathode of the diode DI.sub.1 is connected to the current source IB.sub.1. The collector of the transistor T.sub.11 is grounded. The base of the transistor T.sub.11 is connected to a terminal Y.sub.1 which is adapted to receive a column selection signal. The other bit driver circuits have a circuit configuration similar to the bit driver circuit BD.sub.1.
BSW.sub.1, . . . , and BSW.sub.n represent bit selection circuits. The bit selection circuit BSW.sub.i consits of four transistors T.sub.2i, T.sub.3i, T.sub.4i, and T.sub.5i, where i represents the column number. The collector of the transistor T.sub.2i is connected to the bit line B.sub.i1. The collector of the transistor T.sub.5i is connected to the bit line B.sub.i2. The collector of the transistor T.sub.3i is connected to the coupled emitters of the transistors T.sub.7i and T.sub.8i. The collector of the transistor T.sub.4i is connected to the base of the pull-up transistor T.sub.6i. The emitters of the transistors T.sub.2i through T.sub.5i are connected through signal lines K.sub.2, K.sub.3, K.sub.4, and K.sub.5 to current sources I.sub.2, I.sub.3, I.sub.4, and I.sub.5, respectively. The bases of the transistors T.sub.2i, T.sub.3i, T.sub.4i, and T.sub.5i are commonly connected to a node YB.sub.i connected to the cathode of the diode DI.sub.i. Thus, the transistors T.sub.21, T.sub.22, . . . , and T.sub.2n constitute a current switch. Similarly, the other sets of transistors T.sub.31 through T.sub.3n, T.sub.41 through T.sub.4n, and T.sub.51 through T.sub.5n constitute current switches, respectively. When one of the columns C.sub.i is selected, a high potential column selecting signal is applied through the terminal Y.sub.i to the bases of the transistors T.sub.2i through T.sub.5i in the corresponding bit selection circuit BSW.sub.i so that these transistors are turned on to supply currents to the column C.sub.i.
The operation of the conventional static bipolar RAM of FIG. 1 will now be briefly described. Assume that information is stored in the memory cell MC.sub.11 in a state that the transistor Q.sub.21 is in a conductive state and the transistor Q.sub.22 is in a cut-off state. In this state, the potential V.sub.c1 at the collector of the transistor Q.sub.11 (see FIG. 1B) is at a low potential (hereinafter referred to as an "L level"), and the potential V.sub.c2 at the collector of the transistor Q.sub.12 is at a high potential (hereinafter referred to as a "H level"). When the memory cell MC.sub.11 is selected by applying the H level signals to a terminal X.sub.1 connected to the base of the transistor TW.sub.1 and to the terminal Y.sub.1 connected to the base of the transistor T.sub.11, respectively, the transistor TW.sub.1 is turned on so that the positive word line WD.sub.1.sup.+ is caused to be the H level, and, simultaneously, the transistor T.sub.11 is turned on so that the node YB.sub.1 is caused to be the H level. The other terminals Y.sub.2, . . . , and Y.sub.n are all at the L level so that the nodes YB.sub.2, . . . , and YB.sub.n are at the L level. Accordingly, only the transistors T.sub.21, T.sub.31, T.sub.41, and T.sub.51 is the selected bit selection circuit BSW.sub.1 are turned on to supply currents from the current sources I.sub.2, I.sub.3, I.sub.4, and I.sub.5 to the selected column C.sub.1.
The emitter of the transistor TR.sub.11 for setting the reading reference potential and the emitters of the driving transistors Q.sub.11 in the memory cells MC.sub.11, . . . , and MC.sub.m1 are connected to the bit line B.sub.11 to which the current I.sub.2 is supplied when the transistor T.sub.21 is turned on. Also, the emitter of the transistor TR.sub.12 for setting the reading reference potential and the emitters of the driving transistors Q.sub.12 in the memory cells MC.sub.11, . . . , and MC.sub.m1 are connected to the bit line B.sub.12 to which the current I.sub.5 is supplied when the transistor T.sub.51 is turned on. In the memory cell MC.sub.11, when the positive word line WD.sub.1.sup.+ is raised to the H level so that the potential difference between the positive word line WD.sub.1.sup.+ and the node V.sub.c1 exceeds the threshold voltage of the diode D.sub.1, the diode D.sub.1 begins to conduct current because the node V.sub.c1 was at the L level. In contrast, the diode D.sub.2 is kept in the cut-off state because the node V.sub.c2 was at the H level. When the memory cell MC.sub.11 has been selected, the potential at the nodes V.sub.c1 and V.sub.c2 become higher than those when the memory cell MC.sub.11 is not selected. Also, the potential difference between the nodes V.sub.c1 and V.sub.c2 is increased. Then, the reading reference potential setting circuit RC provides an intermediate potential between the voltages V.sub.c1 and V.sub.c2 to the bases of the transistors TR.sub.11, TR.sub.12, . . . , TR.sub.n1, and TR.sub.n2. Because the base potential of the transistor Q.sub.11 is V.sub.c2, which is higher than the base potential of the transistor TR.sub.11, the current switch constituted by the transistors TR.sub.11 and Q.sub.11 is operated to cause the transistor Q.sub.11 to be turned on, while the transistor TR.sub.11 is kept in the cut-off state. Also, because the base potential of the transistor Q.sub.12 is V.sub.c1, which is lower than the base potential of the transistor TR.sub.12, the current switch constituted by the transistors TR.sub.12 and Q.sub.12 is operated to cause the transistor TR.sub.12 to be turned on, while the transistor Q.sub.12 is kept in the cut-off state. Thus, the transistor Q.sub.11 conducts a current from the positive word line WD.sub.1.sup.+ to the bit line B.sub.11, and the transistor TR.sub.12 conducts current to the bit line B.sub.12. The potential difference between the bit lines B.sub.11 and B.sub.12 is amplified by the pre-sense amplifier PSA.sub.1 which consists of the transistors T.sub.71 and T.sub.81 having emitters commonly connected through the transistor T.sub.31 to the current source I.sub.3 to form a current switch. The amplified signal obtained between the collectors of the transistors T.sub.71 and T.sub.81 is further amplified by the sense amplifier SA.
In order to avoid unnecessary writing in the half-selected memory cells MC.sub.12, . . . , and MC.sub.1n, the driving transistors in these half-selected memory cells must be completely turned off. For this purpose, the pull-up circuits PLP.sub.2, . . . , PLP.sub.n operate so that the transistors T.sub.62, . . . , and T.sub.6n included therein are turned on. Thus, the transistors T.sub.42, . . . , and T.sub.4n are cut off, and, therefore, the bases of the transistors T.sub.62, . . . , and T.sub.6n are at the H level. Thus, the bit lines B.sub.21, B.sub.22, . . . , B.sub.n1, and B.sub.n2 are charged up to the H level by the power supply line V.sub.cc through respective transistors T.sub.62, . . . , and T.sub.6n. This ensures the cut-off states of the driving transistors in the memory cells MC.sub.12, . . . , and MC.sub.1n.
The problem in the conventional static bipolar RAM of FIG. 1A will now be described. Referring to the bit selection circuit BSW.sub.i (i=1, 2, . . . , or n), when one column C.sub.i is selected, a column selection signal is applied to the node YB.sub.i commonly connected to the bases of the transistors T.sub.2i, T.sub.3i, T.sub.4i, and T.sub.5i in the bit selection circuit. When the column changes its state from a nonselected state to a selected state, the column selection signal rises from the L level to the H level. When the column changes its state from a selected state to a nonselected state, the column selection signal falls from the H level to the L level. In the conventional memory, there is a disadvantage in that the falling speed of the potential at the node YB.sub.i is low, so that the switching speed of the columns is low.
More specifically, the bit driver circuit BD.sub.i provided in each column comprises an emitter follower transistor T.sub.1i, a level shifting diode DI.sub.i, and a level shifting current source IB.sub.i. When the potential at the terminal Y.sub.i is at the H level, the transistor T.sub.1i turns on to cause the node YB.sub.i to be at the H level. When the terminal Y.sub.i is at the L level, the transistor T.sub.1i turns off so that the node YB.sub.i goes to the L level. The H level at the node YB.sub.i is set by the transistor T.sub.1i and the diode DI.sub.i to a predetermined level lower than the potential at the collector of the transistor T.sub.2i, T.sub.3i, T.sub.4i, or T.sub.5i, so that the transistors T.sub.2i, T.sub.3i, T.sub.4i, and T.sub.5i are not saturated. The bases of the transistors T.sub.2i, T.sub.3i, T.sub.4i, and T.sub.5i, the junction portion of the diode DI.sub.i, and the wiring line for these bases have a parasitic capacitance CB.sub.i. When the column C.sub.i changes its state from a selected state to a nonselected state, the transistor T.sub.1i is turned off so that the potential at the node YB.sub.i falls. During the fall of the potential at the node YB.sub.i, the charges stored in the parasitic capacitance CB.sub.i should be discharged. Recent technology has increased memory capacities more and more with a corresponding increase in the number of the columns. The increase in the number of columns has been accompanied by an increase in the number of the current sources IB.sub.i as well, so that the power consumption tends to be increased. Also, the lengths of the wiring lines tend to become longer, so that the parasitic capacitance tends to increase. In order to suppress the increase in the power consumption, the value of the current source IB.sub.i should be as small as possible. However, the smaller the value of the current source IB.sub.i, the longer the time required for discharging the parasitic capacitance CB.sub.i. Accordingly, the falling speed of the potential at the node YB.sub.i becomes low.
FIG. 2 is a time chart illustrating the changes of the potentials of the bit lines. In FIG. 2, 1 represents a curve of the potential at the node YB.sub.i when the column C.sub.i changes from its selected state to the nonselected state. As can be seen from the curve 1 , the falling time T is too long. A curve 2 is the curve of the potential at the node YB.sub.i when the column changes from its nonselected state to the selected state. As can be seen from the curve 2 , the rising time T.sub.1 is relatively small regardless of the value of the current IB.sub.i because the emitter-follower transistor T.sub.1i forces the node YB.sub.i to be driven to the H level. In a reading operation, the sense amplifier SA can detect, through the pre-sense amplifier, the potential difference between the bit lines B.sub.i1 and B.sub.i2 only after the potential difference between the curves 1 and 2 exceeds a predetermined value .DELTA.V. Therefore, the falling speed of the potential at the node YB.sub.i directly affects the access time of the memory.
The above-mentioned problem becomes more and more serious with the increase in the memory capacity, because the value of the current source IB.sub.i must be increasingly minimized so as to save on power consumption, along with the increase in the number of columns.